Modern Experimental Techniques – Physics

Workshop 2 β€” Designing printed circuit boards Β· Fri 18 Sep 2026 Β· 14:20–16:20 Β· R311, IAMS

Workshop 2 β€” Designing printed circuit boards

Outline.

Be creative!

Hard cutoff: Monday 28 September, 2 pm. The final Gerber files (the manufacturing files for the board) must be sent for manufacturing then. A late section cannot be on the board.

Prerequisite: between the workshops you improved your Project 1 and Project 2 apps; for today, KiCad 10 installed and opened once, and a JLCPCB account (the board factory; parts come from its own parts library).

Detailed plan (draft β€” follows the workshop outline above)

The hardware model: dev board + carrier, assembled by JLCPCB

The MCU (microcontroller, the small computer on a chip) stays on the proven ESP32-S3 dev board (the board that carries it, with a USB-C connector and pins); the class board is a carrier it plugs into β€” the analog front end done properly, isolation, buffers, robust connectors β€” and the NMR console that makes it an experiment rather than a box. One design, one order, one assembled board per student. JLCPCB assembles everything, surface-mount and through-hole; the main board is 180 Γ— 100 mm, 4 layers, and the front panel is a second board of the same size that mounts flat on the back of it, parallel to it, on three 2Γ—20 pin headers the instructor solders. The panel's outer face is the face of the instrument: 16 SMA connectors in a 3 Γ— 6 grid, the screw terminals for the eight TTL lines, the TX coil terminal, a Qwiic connector, the OLED, the three LEDs, the two isolated inputs and the module header, all pointing up out of it; the main board's rear edge is the back, where the power and coil wiring goes in. You solder nothing, and the dev board alone keeps running the app as the permanent fallback. Fully assembled, the board costs about US$100 per student.

SectionOwnerWhat is in it
Baseinstructordev-board socket, bus distribution, power entry and rails, the external 7–18 V input, and the H-bridge and MOSFET switch (the polarizer switch) that drive the field coils, RGB LED, one Qwiic inside, 2Γ—10 expansion header, and the three 2Γ—20 headers that join the front panel to the main board
A β€” inputs and the NMR receiverstudentEverything the board listens with: the ADS8688 with its eight Β±10 V 16-bit inputs and their protection networks, and the NMR receiver β€” tuned coil input, blanking switch, low-noise preamplifier, I/Q mixer and audio filters into ADC channels 7 and 8, with the Si5351 clock.
B β€” signal generation, timing and the NMR transmitterstudentEverything the board speaks with: the DAC8563 and its Β±10 V output stages (AO1, AO2), the AD9834 synthesizer and OPA564 power amplifier that drive the NMR coil, the 8 TTL outputs, the 2 fast trigger outputs and the switchable TRIG.
C β€” the front panel boardstudentThe face of the instrument, on a 4-layer board of its own (180 Γ— 100 mm): 3 Γ— 6 SMA at 18 mm β€” AO1 AO2 TRIG AUX TX FAST1 / AI1 AI2 AI3 AI4 RX FAST2 / AI5 AI6 AI7 AI8 SPARE (17 fitted, one position blank) β€” the OLED, the three LEDs, the TTL screw-terminal strip, the TX coil terminal, the Qwiic, the 2 fast opto-isolated inputs (5–24 V), and the module header: seven 5 V TTL lines MODULE OUT 1–7 (and one reserved spare pin) with +5 V and ground, through their 5 V buffer, for driving opto-isolated modules.

Every IC on the board is met in class, and every part of the NMR console is fitted β€” nothing on this board is a do-not-populate option. The base β€” the socket, the buses and the power rails, where one mistake would stop every board β€” stays with the instructor.

Electronics 101 β€” six ideas, each pointed at our schematic

(a) Rails, decoupling, ground

Where the power comes from and how it is cleaned up next to every chip; the one place analog and digital ground meet. The base rails, and the decoupling inside every section.

(b) What Β±10 V and 16 bits buy

Range and resolution on the input and output side, and why the dev board's own ADC and DAC (analog-to-digital and digital-to-analog converters) are not enough. Sections A and B.

(c) The op-amp stage as a black box

Gain and offset without the internals: how the DAC's output becomes a Β±10 V swing. Section B.

(d) Isolation

Opto-coupler, creepage distance: sensing and switching things that must not share your ground. Keep 2.5 mm of creepage at the isolated inputs. Section C.

(e) 3.3 V vs 5 V logic

Why a GPIO (a general-purpose pin on the microcontroller) cannot drive 5 V TTL directly and what the buffers do. Section B.

(f) The buses

SPI and IΒ²C (two common wiring standards for chips to talk to the microcontroller) tie the sections to the MCU; which pins carry the fastest signals in your section.

PCB design with KiCad β€” the only six operations

Six operations

Place a part and wire it Β· annotate Β· Update PCB from schematic Β· drag footprints into place Β· route (draw the copper tracks) Β· DRC (KiCad's design-rule check), then the 3D view. Shown live once on the projector, in the base sheet.

Where parts come from

LCSC part numbers on every symbol (a part's drawing in the schematic); easyeda2kicad pulls symbol, footprint and 3D model; JLCPCB places what LCSC stocks. That is automated production and assembly.

Pull request + peer review

One pull request (a request to merge your changes into the shared project; someone reviews it first) for your section, one review of a classmate's from the checklist, one round of fixes β€” the same list the instructor uses at merge.

The class board in class

StepWhat happens
Read your sectionThe tutor asks two questions on your section ("which pins carry the fastest signal?", "where does your section's ground join the rest?"); then a short chat with the neighbour who will review your pull request.
KiCad liveOn the projector, in the base sheet: place a 100 nF + 10 Β΅F pair and wire it, annotate, Update PCB from schematic, drag the two footprints, route three tracks, run DRC, show the 3D view.
E6: schematic gapsOpen your gapped sheets; from the full schematic PDF, place the 3–4 parts missing from each sheet of your section (values and footprints from the project library), wire them, run ERC (KiCad's electrical rule check). The tutor names the parts and checks each placement. Done when ERC shows 0 errors.
E7 (start): route your zoneUpdate PCB from schematic; the new footprints land in your zone (the outlined region of the board that is yours); route; DRC. The tutor reminds you of the rules (nothing on layer 2, stay inside your zone, ZONE_A, ZONE_B or ZONE_C, decoupling next to the pin) and reads the DRC output with you. The instructor fixes the two classic problems live (wrong layer, unconnected net β€” a net is a set of pins that must be connected together).
Pull request + review, liveThe instructor opens a pull request from a student branch, requests the ring reviewer (A reviews B, B reviews C, C reviews A), writes one comment against the checklist, shows "request changes" vs "approve".
Firmware and softwareHow the instrument's firmware and phone app (from Project 2) grow with the board: one driver and one app panel per section. Can you adapt it to solve a problem in your current research?

Between workshops β€” what must be finished for the cutoff (Monday 28 September, 2 pm): E7–E10

Before the next workshop: complete the preparation, improve your apps, build and have fun. The preparation this time: the steps your section needs before the Gerber files go to the factory. A section that is not merged by the cutoff is not on the board.

Peer-review checklist (workbook ch. C β€” the same list the instructor uses at merge): ERC 0 / DRC 0 Β· LCSC field on every part Β· values match the PDF Β· decoupling next to the pins Β· nothing on layer 2 Β· nothing outside your zone Β· pin 1 marked Β· ground pour joined Β· creepage β‰₯ 2.5 mm in section C Β· silkscreen label on every connector Β· CI green (continuous integration: the automatic build GitHub runs on every pull request passes).

Class order: your section must be merged before the cutoff, Monday 28 September, 2 pm. Then the instructor merges the sections into main, runs the full DRC, exports the Gerbers, BOM (parts list) and CPL (placement list) and orders the assembled boards, bare boards and front panels from JLCPCB. Friday 25 September is a public holiday (no class).

Materials